1. Field of Invention
The present invention relates to semiconductor device packages and methods for fabricating the same. More particularly, at least one embodiment is directed to a flip chip semiconductor device package and packaging method.
2. Discussion of Related Art
Presently, there are several semiconductor packaging techniques that are well received in the radio frequency (RF) component industry. However, these packaging techniques are relatively complex and make meeting cost and operational requirements difficult, especially as operating frequencies move higher and size becomes critical.
One widely used packaging technique is the “chip and wire” packaged die, which includes an encapsulated die coupled to a package carrier. The package carrier, either a substrate or metal lead frame, provides the connection from the die to the exterior of the package. In standard chip and wire packaging, the interconnection between the die and the carrier is made using bond wires. The die is attached to the carrier face up, and a wire is bonded first to the die, then looped and bonded to the carrier. Chip and wire packaged dies suffer from relatively large size and parasitic inductances, as well as having manufacturing problems with certain substrate materials.
An example of a chip and wire packaged die 100 is illustrated in FIG. 1. The die 102 is attached face up to a package carrier 104, including a metal lead frame 106, by bond wires 108. The bond wires are typically about 1-5 millimeters (mm) in length. As can be seen in FIG. 1, the lead frame 106 extends substantially beyond the edges of the die 102 in the horizontal direction. This contributes to the relatively large size of chip and wire packaged die. Even if the die itself is small, the “keep out” area (i.e., area in which no other components may be placed) on the substrate or PCB to which the die is to be attached is much larger as it must also accommodate the lead frame. Furthermore, the bond wires 108 used to connect the die to the lead frame cause series parasitic inductances due to the wire diameter and length, which may be detrimental to the overall electrical and/or RF performance of the component. A further disadvantage of the chip and wire package is that the active devices on the die 102 are separated from the carrier 104 (which may comprise a ground and/or cooling plate) by the full thickness of the die substrate. As shown in FIG. 1, a device 110 (such as a field effect transistor) is located on the upper surface of the die, far from the carrier 104, which makes thermal management of the device 110 more difficult. A common solution is to connect the device 110 to the carrier 104 by vias 112. This solution is acceptable in silicon substrates, although it does add to manufacturing complexity. However, Gallium arsenide (GaAS) substrates are very brittle and can easily break when vias, particularly a large number of vias, are drilled through the substrate.
An alternative packaging technique to the standard chip and wire package, is flip chip packaging. Flip chip describes the method of electrically connecting the die to the package carrier. In contrast to standard chip and wire packaging that uses bond wires to connect the die to the carrier, the interconnection between the die and the carrier in flip chip packaging is made through a conductive “bump” that is placed directly on the die surface. The bumped die is then “flipped over” and placed face down with the bumps connecting the die to the carrier directly. Flip chip packaging may often be used with ball grid array (BGA) type packaging. In the BGA type package, the side of the carrier opposite to that on which the die is attached has an array (generally in a grid formation) of solder balls attached thereto. This array of solder balls (or bumps) replaces the metal lead frame of a standard package.
An example of a flip chip BGA package is illustrated in FIG. 2. The die 102 is coupled to the carrier 104 which may be typically a rigid laminate or similar structure. The carrier 104 may include a ground and/or cooling plate (not shown). The flip chip connection between the die 102 and carrier 104 is generally formed in one of two ways: using conductive adhesive or, more commonly, solder. In case of solder connections, the bumped die, with solder bumps 114, is attached to the carrier 104 by a solder reflow process, very similar to the process used to connect the BGA balls 116 to the package exterior. Vias 120 may be used to interconnect the solder bumps 114 (i.e., die connections) with the balls 116 of the BGA, so as to allow connections to the die from the exterior of the package. After the die is soldered, an underfill 118, generally an epoxy, is added between the die 102 and the carrier 104. The epoxy underfill 118 is used to control the stress in the solder joints caused by the difference in thermal expansion between the die 102 (generally silicon or GaAs) and the carrier 104.
In the flip chip design, the device 110 is very close to the carrier 104, which as discussed above may include a ground/cooling plate, making thermal management easier. In addition, the chip is directly coupled to the carrier 104, eliminating the parasitic inductances associated with the bond wire connections of chip and wire packages. Flip chip BGAs have seen acceptance in the silicon arena, but are disfavored in the GaAs analog arena, largely due to added size of the BGA pattern, particularly caused by limits in bump to bump spacing, and the fragile GaAs material.